View CY7C443-12JI_650007.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

43
CY7C441 CY7C443
Clocked 512 x 9, 2K x 9 FIFOs
Features
* High-speed, low-power, first-in first-out (FIFO) memories * 512 x 9 (CY7C441) * 2,048 x 9 (CY7C443) * 0.65 micron CMOS for optimum speed/power * High-speed 83-MHz operation (12 ns read/write cycle time) * Low power -- ICC=70 mA * Fully asynchronous and simultaneous read and write operation * Empty, Almost Empty, and Almost Full status flags * TTL compatible * Parity generation/checking * Independent read and write enable pins * Supports free-running 50% duty cycle clock inputs * Center power and ground pins for reduced noise * Width Expansion Capability * Available in PLCC packages lutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. Both FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a free-running read clock (CKR) and a read enable pin (ENR). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are acceptable. The CY7C441 and CY7C443 clocked FIFOs provide two status flag pins (F1 and F2). These flags are decoded to determine one of four states: Empty, Almost Empty, Intermediate, and Almost Full (Table 1). The flags are synchronous; i.e., change state relative to either the read clock (CKR) or the write clock (CKW). The Empty and Almost Empty states are updated exclusively by the CKR while Almost Full is updated exclusively by CKW. The synchronous flag architecture guarantees that the flags maintain their status for some minimum time. The CY7C441 and the CY7C443 use center power and ground for reduced noise. Both configurations are fabricated using an advanced.65m CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by reliable layout techniques and guard rings.
Functional Description
The CY7C441 and CY7C443 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a 512 word by 9 bit memory array, while the CY7C443 has a 2048 word by 9 bit memory array. These devices provide so-
Logic Block Diagram
CKW ENW D0- 8
Pin Configuration
PLCC Top View
INPUT REGISTER WRITE CONTROL LOGIC FLAG LOGIC F1 F2 D0 ENW CKW VCC VSS F1 F2 NC Q0 D 1 D 2 D 3 NCD 4 D 5 D 6 4 3 2 1 32 31 30 29 28 27 26 7C441 25 7C443 24 23 22 21 14 15 16 17 1819 20 D7 D8 NC MR VSS CKR ENR Q8 Q7 C441-2
WRITE POINTER
RAM ARRAY 512 x 9 2048x 9
READ POINTER
5 6 7 8 9 10 11 12 13
MR
RESET LOGIC
READ CONTROL LOGIC
Q1 Q 2 Q 3 NC Q 4 Q5 Q 6
OUTPUT REGISTER
CKR Q0- 8
ENR C441-1
Cypress Semiconductor Corporation Document #: 38-06032 Rev. *A
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 26, 2002
CY7C441 CY7C443
Selection Guide
7C441-12 7C443-12 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Clock HIGH Time (ns) Minimum Clock LOW Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Maximum Current (mA) Commercial Military/Industrial Selection Guide (continued) CY7C441 Density Package 512 x 9 32-Pin PLCC CY7C443 2,048 x 9 32-Pin PLCC Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... > 200 mA 83.3 9 12 5 5 4 0 9 140 150 7C441-14 7C443-14 71.4 10 14 6.5 6.5 5 0 10 140 150 7C441-20 7C443-20 50 15 20 9 9 6 0 15 120 130 7C441-30 7C443-30 33.3 20 30 12 12 7 0 20 100 110
Maximum Ratings[1](Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V Output Current into Outputs (LOW) .............................20 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Pin Definitions
Signal Name D0-8 Q0-8 ENW ENR CKW CKR F1 F2 MR I/O I O I I I I O O I Description Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge) writes data (D0 - D8) into the FIFO's memory Data Outputs: when the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0 - Q8) out of the FIFO's memory Enable Write: enables the CKW input Enable Read: enables the CKR input Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and updates the Almost Full flag state Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW and updates the Almost Empty and Empty flag states Flag 1: is used in conjunction with Flag 2 to decode which state the FIFO is in (see Table 1) Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in (see Table 1) Master Reset: resets the device to an empty condition
Document #: 38-06032 Rev. *A
Page 2 of 15
CY7C441 CY7C443
Electrical Characteristics Over the Operating Range
7C441-12 7C443-12 Parameter VOH VOL VIH VIL IIX IOS[2] ICC1[3] ICC2
[4]
7C441-14 7C443-14 2.4
7C441-20 7C443-20 2.4
7C441-30 7C443-30 2.4 V 0.4 2.2 -0.5 -10 -90 VCC 0.8 +10 V V V
Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Short Circuit Current Operating Current Operating Current Standby Current
Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA
Min. Max. Min. Max. Min. Max. Min. Max. Unit 2.4 0.4 2.2 -0.5 VCC 0.8 +10 2.2 -0.5 -10 -90 140 150 70 80 30 30 140 150 70 80 30 30
0.4 VCC 0.8 +10 2.2 -0.5 -10 -90
0.4 VCC 0.8 +10
VCC = Max., GND < VI < VCC VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA VCC = Max., IOUT = 0 mA VCC = Max., IOUT = 0 mA Com'l Mil/Ind Com'l Mil/Ind Com'l Mil/Ind
-10 -90
A
mA
120 130 70 80 30 30
100 110 70 80 30 30
mA mA mA mA mA mA
ISB[5]
Capacitance[6]
Parameter CIN Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 Unit pF
AC Test Loads and Waveform[7,8]
R1 500 5V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT 200 OUTPUT R2 333 3.0V GND 3 ns
C441-4
ALL INPUT PULSES 90% 10% 90% 10% 3 ns
C441-5
2V
Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Test no more than one output at a time and do not test any output for more than one second. 3. Input signals switch from 0V to 3V with a rise/fall time of 3 ns or less, clocks and clock enables switch at maximum frequency (fMAX), while data inputs switch at fMAX/2. Outputs are unloaded. 4. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 5. All inputs signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX). 6. Tested initially and after any design or process changes that may affect these parameters. 7. CL = 30 pF for all AC parameters. 8. All AC measurements are referenced to 1.5V.
Document #: 38-06032 Rev. *A
Page 3 of 15
CY7C441 CY7C443
Switching Characteristics Over the Operating Range[9]
7C441-12 7C443-12 Parameter tCKW tCKR tCKH tCKL tA[10] tOH tFH tSD tHD tSEN tHEN tFD tSKEW1 tPMR tSCMR tOHMR tMRR tMRF tAMR
[11]
7C441-14 7C443-14 Min. 14 14 6.5 6.5 Max.
7C441-20 7C443-20 Min. 20 20 9 9 Max.
7C441-30 7C443-30 Min. 30 30 12 12 Max. Unit ns ns ns ns 20 0 0 7 0 7 0 ns ns ns ns ns ns ns 20 0 30 30 0 0 30 ns ns ns ns ns ns ns 30 30 ns ns
Description Write Clock Cycle Read Clock Cycle Clock HIGH Clock LOW Data Access Time Previous Output Data Hold After Read HIGH Previous Flag Hold After Read/Write HIGH Data Set-Up Data Hold Enable Set-Up Enable Hold Flag Delay Opposite Clock After Clock Opposite Clock Before Clock Master Reset Pulse Width (MR LOW) Last Valid Clock LOW Set-Up to MR LOW Data Hold From MR LOW Master Reset Recovery (MR HIGH Set-Up to First Enabled Write/Read) MR HIGH to Flags Valid MR HIGH to Data Outputs LOW
Min. 12 12 5 5
Max.
9 0 0 4 0 4 0 9 0 12 12 0 0 12 12 12 0 14 14 0 0 14 0 0 5 0 5 0
10 0 0 6 0 6 0 10 0 20 20 0 0 20 14 14
15
15
tSKEW2[12]
20 20
Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in the AC Test Loads and Waveforms and capacitance as in Note 7, unless otherwise specified. 10. Access time includes all data outputs switching simultaneously. 11. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full flag. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Almost Full flag, CKR is the clock for Empty and Almost Empty flags. 12. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEW2 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. See Note 11 for definition of clock and opposite clock.
Document #: 38-06032 Rev. *A
Page 4 of 15
CY7C441 CY7C443
Switching Waveforms
Write Clock Timing Diagram
tCKW tCKH CKW tSD D0 - 8
VALID DATA IN ENABLED WRITE
tCKL
DISABLED WRITE
tHD
tSEN ENW tFH F1
tHEN
tSEN
tHEN
tFD
tFH
tFD
C441-6
Read Clock Timing Diagram
tCKH CKR tCKR tCKL
DISABLED READ
ENABLED READ
tOH Q0 - 8
PREVIOUS WORD
tA
NEW WORD
tSEN ENR tFH F1, F2
tHEN
tSEN
tHEN
tFD
tFH
tFD
C441-7
Document #: 38-06032 Rev. *A
Page 5 of 15
CY7C441 CY7C443
Switching Waveforms (continued)
Master Reset Timing Diagram[13, 14, 15, 16]
tPMR MR tSCMR CKW tMRR
ENW tSCMR CKR tMRR
ENR tOHMR Q0 - 8 VALID DATA tMRF F1, F2
C441-8
tAMR ALL DATA OUTPUTS LOW
Read to Empty Timing Diagram
COUNT 3 2
[17, 18, 19]
1 0 1 1 (no change) LATENT CYCLE 0
CKR
R1 ENABLED READ
R2 ENABLED READ
R3 ENABLED READ
R4 FLAG UPDATE READ
R5 ENABLED READ
ENR tSKEW1 CKW ENW LOW tFD F1 F2 LOW
C441-10
tSKEW2
W1 ENABLED WRITE
tFD
tFD
Notes: 13. ENW or CKW must be inactive while MR is LOW. 14. ENR or CKR must be inactive while MR is LOW. 15. All data outputs (Q0 - 8) go LOW as a result of the rising edge of MR. 16. In this example, Q0 - 8 will remain valid until tOHMR if the first read shown did not occur or if the read occurred soon enough such that the valid data was caused by it. 17. "Count" is the number of words in the FIFO. 18. CKR is clock and CKW is opposite clock. 19. R3 updates the flags to the Empty state by bringing F1 LOW. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating flag status. But because W1 occurs greater than tSKEW2 before R4, R4 includes W1 in the flag update and therefore updates the FIFO to the Almost Empty state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status, regardless of the state of ENR. It does not change the count or the FIFO's data outputs.
Document #: 38-06032 Rev. *A
Page 6 of 15
CY7C441 CY7C443
Switching Waveforms (continued)
Read to Empty Timing Diagram with Free-Running Clocks
COUNT 1 0 1
[17, 18, 20]
LATENT CYCLE
0
CKR
R1 ENABLED READ
R2 IGNORED READ
R3 IGNORED READ
tSKEW2 ENR tSKEW1 CKW
W1 W2
tSKEW2
R4 FLAG UPDATE READ
R5 ENABLED READ
R6 IGNORED READ
tSKEW2
W3 ENABLED WRITE W4 W5 W6
ENW tFD F1 F1 F2 F2 LOW
C441-9
tFD
tFD
Read to Almost Empty Timing Diagram with Free-Running Clocks[17, 18]
COUNT 17 16 17 18 17 16 15
CKR
R1 ENABLED READ
R2
R3
R4 ENABLED READ
R5 ENABLED READ
R6 ENABLED READ
ENR tSKEW1 CKW
W1
W2 ENABLED WRITE
tSKEW2
W3 ENABLED WRITE
W4
W5
W6
ENW
F1
HIGH tFD tFD tFD
F2
C441-11
Note: 20. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than tSKEW2 before R4, R4 includes W3 in the flag update.
Document #: 38-06032 Rev. *A
Page 7 of 15
CY7C441 CY7C443
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Read Flag Update Cycle and Free-Running Clocks[17, 18, 21, 22]
18 (no change) COUNT 17 16 17 18 FLAG UPDATE CYCLE 17 16 15
CKR
R1 ENABLED READ
R2
R3
R4 FLAG UPDATE READ
R5 ENABLED READ
R6 ENABLED READ
R7 ENABLED READ
ENR tSKEW1 CKW
W1 W2 ENABLED WRITE
tSKEW2
W3 ENABLED WRITE W4
W5
W6
W7
ENW
F1
HIGH tFD tFD tFD
F2
C441-12
Write to Almost Full Timing Diagram
COUNT 2030 [494] 2031 [495]
[17, 23, 24, 25, 26]
2032 [496]
2031 [495]
2030 [494]
2031 [497] 2030 [494]
2032 [498] 2031 [495]
2033 [497] 2032 [498]
CKW
W1 ENABLED WRITE
W2 ENABLED WRITE
W3 ENABLED WRITE FLAG UPDATE
W4 ENABLED WRITE
W5 ENABLED WRITE
ENW
LOW tSKEW1 tSKEW2
R1 ENABLED READ R2 ENABLED READ
CKR LOW tFD F1
ENR
tFD
tFD
tFD
F2
HIGH
C441-14
Notes: 21. R4 only updates the flag status. It does not affect the count because ENR is HIGH. 22. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 A18; two enabled writes: W2, W3) before a read (R4) can update flags to the Intermediate state. 23. CKW is clock and CKR is opposite clock. 24. Count = 2032 indicates Almost Full for CY7C443 and count = 496 indicates Almost Full for CY7C441. Values for the CY7C441 count are shown in brackets. 25. The dashed lines show W3 as flag update write rather than an enabled write because ENW is deasserted. 26. W2 updates the flags to the Almost Full state by bringing F1 LOW. Because R1 occurs greater than tSKEW1 after W2, W2 does not recognize R1 when updating the flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does not have to be enabled to update flags.
Document #: 38-06032 Rev. *A
Page 8 of 15
CY7C441 CY7C443
Switching Waveforms (continued)
Write to Almost Full
COUNT 2031 [495] 2032 [496] W1 ENABLED WRITE
Timing Diagram with Free-Running Clocks
2031 [495] 2030 [494]
[17, 23, 24]
2031 [495] W4 ENABLED WRITE
2032 [496] W5 ENABLED WRITE
2033 [497] W6 ENABLED WRITE
CKW
W2
W3
ENW tSKEW1 CKR
R1 R2 ENABLED READ
tSKEW2
R3 ENABLED READ R4 R5 R6
ENR tFD F1 tFD tFD
F2
HIGH
C441-13
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks[17, 23, 24, 27]
COUNT 2031 [495] 2032 [496] W1 ENABLED WRITE 2031 [495] W2 2030 [494] W3 2030 (no change) [494] FLAG UPDATE CYCLE 2031 [495] W5 ENABLED WRITE 2032 [496] W6 ENABLED WRITE 2033 [497] W7 ENABLED WRITE
CKW
W4 FLAG UPDATE WRITE
ENW tSKEW1 CKR
R1
R2 ENABLED READ
tSKEW2
R3 ENABLED READ
R4
R5
R6
R7
ENR tFD F1 F2 HIGH tFD tFD
C441-15
Note: 27. When making the transition from Almost Full to Intermediate, the count must decrease by two (2032 A 2030; two enabled reads: R2, R3) before a write (W4) can update flags to Intermediate state.
Architecture
The CY7C441/443 consist of an array of 512/2048 words of 9 bits each (implemented by an array of dual-port RAM cells), a read pointer, a write pointer, control signals (CKR, CKW, ENR, ENW, MR), and flags (F1, F2).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the Empty condition signified by both flags F1 and F2 being LOW. All data outputs (Q0-8) go LOW at the rising edge of MR. In order for the FIFO to reset to its default state, a falling edge must occur on MR and the user must not read or write while MR is LOW (unless Page 9 of 15
Document #: 38-06032 Rev. *A
CY7C441 CY7C443
ENR and ENW are HIGH). Upon completion of the Master Reset cycle, all data outputs will go LOW tAMR after MR is deasserted. F1 and F2 are guaranteed to be valid tMRF after MR is taken HIGH. synchronous architecture guarantees some minimum valid time for the flags. The Empty and Almost Empty flag states are exclusively updated by each rising edge of the read clock (CKR). For example, when the FIFO contains 1 word, the next read (rising edge of CKR while ENR=LOW) causes the F1 and F2 pins to output a state signifying the Empty condition. The Almost Full flag is updated exclusively by the write clock (CKW). For example, if the CY7C443 FIFO contains 2031 words (2032 words or greater indicates Almost Full in the CY7C443), the next write (rising edge of CKW while ENW=LOW) causes the F1 and F2 pins to output the Almost Full state. Table 1. Flag Truth Table CY7C441 Number of Words in FIFO 0 1 - 16 17 - 495 496 - 512 CY7C443 Number of Words in FIFO 0 1 - 16 17 - 2031 2032 - 2048
FIFO Operation
When the ENW signal is active (LOW), data on the D0-8 pins is written into the FIFO on each rising edge of the CKW signal. Similarly, when the ENR signal is active, data in the FIFO memory will be presented on the Q0-8 outputs. New data will be presented on each rising edge of CKR while ENR is active. ENR must set up tSEN before CKR for it to be a valid read. ENW must occur tSEN before CKW for it to be a valid write. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0-8 outputs even after additional reads occur.
F1 0 1 1 0
F2 0 0 1 1
State Empty Almost Empty Intermediate Range Almost Full or Full
Flag Operation
The CY7C441/3 provide two flags, F1 and F2, which are used to decode four FIFO states (see Table 1). All flags are synchronous, meaning that the change of states is relative to one of the clocks (CKR or CKW, as appropriate; see Figure 1). The
E CKR F1
AF CKW
AE CKR INTERNAL LOGIC Figure 1. Flag Logic Diagram
F2 PINS
C441-16
Flag Operation (continued)
Since the flags denoting emptiness (Empty, Almost Empty) are only updated by CKR and the Almost Full flag is only updated by the CKW, careful attention must be given to the flag operation. The user must be aware that if a flag boundary (Empty, Almost Empty, and Almost Full) is crossed due to an operation from a clock that the flag is not synchronized to (i.e.,CKR does not effect Almost Full), a flag update is necessary to represent the FIFO's new state. This signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty and Almost Empty flags; CKR is the opposite clock for the Almost Full flag). Until the flag update cycle is executed, the synchronous flags do not show the true state of the FIFO. For example, if 2,040 Document #: 38-06032 Rev. *A
writes are performed to an empty CY7C443 without a single read, F1 and F2 will still exhibit an Empty flag. This is because F2 is exclusively updated by the CKR, therefore, a single read (flag update cycle) is necessary to update flags to Almost Full state. It should be noted that this flag update read does not require ENR = LOW, so a free-running read clock will initiate the flag update cycle. When updating the flags, the CY7C441/443 decide whether or not the opposite clock was recognized when a clock updates the flag. For example, if a write occurs at least tSKEW1 after a read when updating the Empty flag, the write is guaranteed not to be included when CKR updates the flag. If a write occurs at least tSKEW2 before a read, the write is guaranteed to be included when CKR updates the flag. If a write occurs within tSKEW1/tSKEW2 after or before CKR, then the decision of Page 10 of 15
CY7C441 CY7C443
whether or not to include the write when the flag is updated by CKR is arbitrary. The update cycle for non-boundary flags (Almost Empty, Almost Full) is different from that used to update the boundary flag (Empty). Both operations are described below. Boundary Flag (Empty) The Empty flag is synchronized to the CKR signal. The Empty flag can only be updated by a clock pulse on the CKR pin. An empty FIFO that is written to will be described with an Empty flag state until a clock pulse is presented on the CKR pin. When making the transition from Empty to Almost Empty (or Empty to Intermediate or Empty to Almost Full), a clock cycle on the CKR is necessary to update the flags to the current state. Such a state (flags displaying empty even though data has been written to the FIFO) would require two read cycles to read data out of FIFO. The first read serves only to update the flags to the Almost Empty, Intermediate, or Almost Full state, and the second read outputs the data. This first read cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in FIFO). It simply deasserts the Empty flag. The flags are updated regardless of the ENR state. Therefore the update occurs even when ENR is deasserted (HIGH) so that a valid read is not necessary to update the flags to correctly describe the FIFO. With a free-running clock connected to CKR, the flag updates with each cycle. Table 2 shows sample operations that update the Empty flag. Although a Full flag is not supplied externally on the CY7C441/CY7C443, a Full flag exists internally. The operation of the FIFO at the Full boundary is analogous to its operation at the Empty boundary. See the text section "Boundary Flags (Full)" in the CY7C451/CY7C453 datasheet. Non-Boundary Flags (Almost Empty, Almost Full) The flag status pins, F1 and F2, exhibit the Almost Empty status when both the CY7C441 and the CY7C443 contain 16 words or less. The Almost Full Flag becomes active when the FIFO contains 16 or less empty locations. The CY7C441 becomes Almost Full when it contains 496 words. The CY7C443 becomes Almost Full when it contains 2032 words. The Almost Empty flag (like the Empty flag) is synchronous to the CKR signal, whereas the Almost Full flag is synchronous to the CKW signal. Non-boundary flags employ flag update cycles similar to the boundary flag latent cycles in order to update the FIFO state. For example, if the FIFO just reaches the Almost Empty state (16 words) and then two words are written, a read clock (CKR) will be required to update the flags to the Intermediate state. However, unlike the boundary (Empty) flag's update cycle, the state of the enable pin (ENR in this case) affects the operation. Therefore, ENR set-up (tSEN) and hold (tHEN) times must be met. If ENR is asserted (ENR=LOW) during the latent cycle, the count and data update in addition to F1 and F2. If ENR is not active (ENR=1) during the flag update cycle, only the flag is updated. The same principles apply for updating the flags when a transition from the Almost Full to the Intermediate state occurs. If the CY7C443 just reaches the Almost Full state (2032 words) and then two words are read, a write clock (CKW) will be required to update the flag to the Intermediate state. If ENW is LOW during the flag update cycle, the count and data update in addition to the flags. If ENW is HIGH, only the flag is updated. Therefore, ENW set-up (tSEN) and hold (tHEN) times must be met. Tables 3 and 4 show examples for a sequence of operations that affect the Almost Empty and Almost Full flags, respectively.
Width Expansion
The CY7C441/3 can be expanded in width to provide word width greater than 9 in increments of 9. During width expansion mode, all control inputs are common. When the FIFO is being read near the Empty boundary, it is important to note that both sets of flags should be checked to see if they have been updated to the Not Empty condition on all devices. Checking all sets of flags is critical so that data is not read from the FIFOs "staggered" by one clock cycle. This situation could occur when the first write to an empty FIFO and a read are very close together. If the read occurs less than tSKEW2 after the first write to two width expanded devices (A and B), device A may go Almost Empty (read recognized as flag update) while device B stays Empty (read ignored).The first write occurs because a read within tSKEW2 of the first write is only guaranteed to be either recognized or ignored, but which of the two is not guaranteed. The next read cycle outputs the first half of the first word on device A while device B updates its flags to Almost Empty. Subsequent reads will continue to output "staggered" data assuming more data has been written to the FIFOs. In the width expansion configuration, any of the devices' flags may be monitored for the composite Almost Full status.
Document #: 38-06032 Rev. *A
Page 11 of 15
CY7C441 CY7C443
Table 2. Empty Flag Operation Example [28] Status Before Operation Current State of FIFO Empty Empty Empty AE AE Empty Empty AE Number of Words in FIFO 0 1 2 2 1 0 1 1 Next State of FIFO Empty Empty AE AE Empty Empty AE Empty
Status After Operation Number of Words in FIFO 1 2 2 1 0 1 1 0 Write Write Flag Update Read Read (Transition for Almost Empty to Empty) Write Flag Update Read (Transition from Almost Empty to Empty)
F1 0 0 0 1 1 0 0 1
F2 0 0 0 0 0 0 0 0
Operation Write (ENW = LOW) Write (ENW = LOW) Read (ENR = HIGH) Read (ENR = LOW) Read (ENR = LOW) Write (ENW = LOW) Read (ENR = X) Read (ENR = LOW)
F1 0 0 1 1 0 0 1 0
F2 0 0 0 0 0 0 0 0
Comments
Table 3. Almost Empty Flag Operation Example[28] Status Before Operation Current State of FIFO AE AE AE Intermediate Number of Words in FIFO 16 17 18 17 Next State of FIFO AE AE Intermediate AE
Status After Operation Number of Words in FIFO 17 18 17 16
F1 1 1 1 1
F2 0 0 0 1
Operation Write (ENW = LOW) Write (ENW = LOW) Read (ENR = LOW) Read (ENR = LOW) Read (ENR = HIGH)
F1 1 1 1 1
F2 0 0 1 0
Comments Write Write Flag Update and Read Read (Transition from Intermediate to Almost Empty) Ignored Read
AE
1
0
16
AE
1
0
16
Note: 28. Applies to both the CY7C441 and CY7C443 operations.
Document #: 38-06032 Rev. *A
Page 12 of 15
CY7C441 CY7C443
Table 4. Almost Full Flag Operation Example[29,30] Status Before Operation Number Number of Words of Words Current State in FIFO in FIFO of FIFO F1 F2 CY7C441 CY7C443 AF AF AF Intermediate Intermediate 0 0 0 1 1 1 1 1 1 1 496 495 494 494 495 2032 2031 2030 2030 2031 Status After Operation Number of Number of Words in Words in FIFO FIFO F1 F2 CY7C441 CY7C443 Comments 0 0 1 1 0 1 1 1 1 1 495 494 494 495 496 2031 2030 2030 2031 2032 Read Read Flag Update Write Write (Transition from Intermediate toAlmost Full)
Operation Read (ENR=LOW) Read (ENR=LOW)
Next State of FIFO AF AF
Write Intermediate (ENW=HIGH) Write (ENW=LOW) Write (ENW=LOW) Intermediate AF
Note: 29. The CY7C441 Almost Full state is represented by 496 or more words. 30. The CY7C443 Almost Full state is represented by 2032 or more words.
Ordering Information
512x9 Clocked FIFO Speed (ns) 12 14 20 30 Ordering Code CY7C441-12JC CY7C441-12JI CY7C441-14JC CY7C441-14JI CY7C441-20JC CY7C441-20JI CY7C441-30JC CY7C441-30JI Package Name J65 J65 J65 J65 J65 J65 J65 J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
2Kx9 Clocked FIFO Speed (ns) 12 14 20 30 Ordering Code CY7C443-12JC CY7C443-12JI CY7C443-14JC CY7C443-14JI CY7C443-20JC CY7C443-20JI CY7C443-30JC CY7C443-30JI Package Name J65 J65 J65 J65 J65 J65 J65 J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Document #: 38-06032 Rev. *A
Page 13 of 15
CY7C441 CY7C443
Package Diagrams
32-Lead Plastic Leaded Chip Carrier J65
Document #: 38-06032 Rev. *A
Page 14 of 15
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C441 CY7C443
Document Title: CY7C441 / CY7C443 Clocked 512 x 9, 2K x 9 FIFOs Document Number: 38-06032 REV. ** *A ECN NO. 110173 122283 Issue Date 09/29/01 12/26/02 Orig. of Change SZV RBI Description of Change Change from Spec number: 38-00124 to 38-06032 Power up requirements added to Maximum Ratings Information
Document #: 38-06032 Rev. *A
Page 15 of 15

▲Up To Search▲

Price & Availability of CY7C443-12JI

	To Download CY7C443-12JI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .